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general description the max1778/max1880?ax1885 multiple-output dc-dc converters provide the regulated voltages required by active matrix thin-film transistor (tft) liquid crystal displays (lcd) in a low-profile tssop package. one high-power step-up converter and two low-power charge pumps convert the 2.7v to 5.5v input voltage into three independent output voltages. a built-in linear regulator and vcom buffer complete the power-supply requirements. the main step-up converter accurately generates an externally set output voltage up to 13v that can supply the display? row/column drivers. the converter? high switching frequency and current-mode pwm architec- ture provide fast transient response and allow the use of small low-profile inductors and ceramic capacitors. the low-power bicmos control circuitry and internal 14v switch (0.35 ? n-channel mosfet) enable efficien- cies up to 91%. the dual low-power charge pumps (max1778/ max1880/max1881/max1882 only) independently reg- ulate one positive output (v pos ) and one negative out- put (v neg ). these low-power outputs use external diode and capacitor stages (as many stages as required) to regulate output voltages up to +40v and -40v. a unique control scheme minimizes output ripple as well as capacitor sizes for both charge pumps. a resistor-programmable, 40ma, low-dropout linear regulator (max1778/max1881/max1883/max1884 only) provides preregulation or postregulation for any of the supplies. for higher current applications, an exter- nal transistor can be added. additionally, the vcom buffer provides a high current output that is ideal for driving the capacitive backplane of tft lcd panels. the vcom buffer? output voltage is preset with an internal 50% resistive-divider or can be externally adjusted for other voltages. the max1778/max1880?ax1885 are protected against output undervoltage and thermal overload con- ditions by a latched fault detection circuit that shuts down the device. all devices are available in the ultra- thin tssop package (1.1mm max height). applications tft lcd notebook displays tft lcd desktop monitor panels features 500khz/1mhz current-mode pwm step-up regulator up to +13v main high-power output ?% accurate high efficiency (91%) dual regulated charge-pump outputs (max1778/max1880/max1881/max1882 only) up to +40v positive charge-pump output up to -40v negative charge-pump output low-dropout 40ma linear regulator (max1778/max1881/max1883/max1884 only) up to +15v ldo input optional higher current with external transistor 2.7v to 5.5v input supply internal supply sequencing and soft-start power-ready output adjustable fault-detection latch thermal protection (+160?) 0.1? shutdown current 0.7ma in quiescent current ultra-small external components thin tssop package (1.1mm max height) max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer ________________________________________________________________ maxim integrated products 1 19-1979; rev 0a; 3/01 ordering information part temp. range pin-package max1778 eug -40 c to +85 c 24 tssop max1880 eug -40 c to +85 c 24 tssop max1881 eug -40 c to +85 c 24 tssop max1882 eug -40 c to +85 c 24 tssop max1883 eup -40 c to +85 c 20 tssop max1884 eup -40 c to +85 c 20 tssop max1885 eup -40 c to +85 c 20 tssop typical operating circuit appears at end of data sheet. pin configurations and selector guide appear at end of data sheet. for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com.
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v in = +3.0v, shdn = in, v supp = v supn = v supb = v supl = 10v, ldoout = fbl, buf- = bufout, buf+ = fltset = tgnd = pgnd = gnd, c ref = 0.22f, c buf = 1f, t a = 0 c to +85 c . typical values are at t a = +25 c, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in, shdn , tgnd, fltset to gnd...........................-0.3v to +6v drvn to gnd .........................................-0.3v to (v supn + 0.3v) drvp to gnd..........................................-0.3v to (v supp + 0.3v) pgnd to gnd.....................................................................0.3v rdy , supb to gnd ................................................-0.3v to +14v lx, supp, supn to pgnd .....................................-0.3v to +14v supl to gnd..........................................................-0.3v to +18v ldoout to gnd ....................................-0.3v to (v supl + 0.3v) intg, ref, fb, fbn, fbp to gnd ...............-0.3v to (v in + 0.3v) fbl to gnd .............-0.3v to the lower of (v sup l + 0.3v) or +6v bufout, buf+, buf- to gnd ...............-0.3v to (v supb + 0.3v) continuous power dissipation (t a = +70 c) 20-pin tssop (derate 10.9mw/ c above +70 c) ......879mw 24-pin tssop (derate 12.2mw/ c above +70 c) ......975mw operating temperature range max1778eug, max1883eup ........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units input supply range v in 2.7 5.5 v input undervoltage threshold v uvlo v in rising, 40mv hysteresis (typ) 2.2 2.4 2.6 v max1778/max1880/ max1883 (f osc = 1mhz) 0.7 1 in quiescent supply current i in v fb = v fbp = 1.5v, v fbn = -0.2v max1881/max1882/ max1884/max1885 (f osc = 500khz) 0.6 1 ma max1778/max1880 (f osc = 1mhz) 0.4 0.7 supp quiescent current i supp v fbp = 1.5v max1881/max1882 (f osc = 500khz) 0.3 0.5 ma max1778/max1880 (f osc = 1mhz) 0.4 0.7 supn quiescent current i supn v fbn = -0.2v max1881/max1882 (f osc = 500khz) 0.3 0.5 ma in shutdown current v shdn = 0, v in = 5v 0.1 10 a supp shutdown current v shdn = 0, v supp = 13v, max1778/max1880/max1881/max1882 0.1 10 a supn shutdown current v shdn = 0, v supn = 13v, max1778/max1880/max1881/max1882 0.1 10 a supl shutdown current v shdn = 0, v supl = 13v max1778/max1881/max1883/max1884 0.1 10 a supb shutdown current v shdn = 0, v supb = 13v 6 13 a
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer _______________________________________________________________________________________ 3 electrical characteristics (continued) (v in = +3.0v, shdn = in, v supp = v supn = v supb = v supl = 10v, ldoout = fbl, buf- = bufout, buf+ = fltset = tgnd = pgnd = gnd, c ref = 0.22f, c buf = 1f, t a = 0 c to +85 c . typical values are at t a = +25 c, unless otherwise noted.) parameter symbol conditions min typ max units main step-up converter main output voltage range v main v in 13 v integrator enabled, c intg = 1000pf 1.234 1.247 1.260 fb regulation voltage v fb integrator disabled (intg = ref) 1.220 1.280 v fb input bias current i fb v fb = 1.25v, intg = gnd -50 +50 na max1778/max1880/max1883 0.85 1 1.15 mhz operating frequency f osc max1881/max1882/max1884/max1885 425 500 575 khz oscillator maximum duty cycle 80 85 91 % integrator enabled, c intg = 1000pf 0.01 load regulation i lx = 0 to 200ma, v main = 10v integrator disabled (intg = ref) 0.2 % line regulation 0.1 %/v integrator transconductance 317 s lx switch on-resistance r lx ( on ) i lx = 100ma 0.35 0.7 ? lx leakage current i lx v lx = 13v 0.01 20 a phase i = soft-start (1024/f osc ) 0.275 0.38 0.5 phase ii = soft-start (1024/f osc ) 0.75 phase iii = soft-start (1024/f osc ) 1.12 lx current limit i lim phase iv = fully-on (after 3072/f osc ) 1.15 1.5 1.85 a maximum rms lx current 1a soft-start period t ss power-up to the end of phase iii 3072 / f osc s falling edge, fltset = gnd 1.07 1.1 1.14 fb fault trip level falling edge, fltset = 1v 0.955 0.99 1.025 v positive charge pump (max1778/max1880/max1881/max1882 only) supp input supply range v supp 2.7 13 v operating frequency f chp 0.5 x f osc hz fbp regulation voltage v fbp 1.2 1.25 1.3 v fbp input bias current i fbp v fbp = 1.5v -50 +50 na drvp pch on-resistance r pch ( on ) 510 ? v fbp = 1.2v 2 4 ? drvp nch on-resistance r nch ( on ) v fbp = 1.3v 20 k ? maximum rms drvp current 0.1 a fbp power-ready trip level rising edge 1.09 1.125 1.16 v falling edge, fltset = gnd 1.08 1.11 1.16 fbp fault trip level falling edge, fltset = 1v 0.955 0.99 1.025 v
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer 4 _______________________________________________________________________________________ electrical characteristics (continued) (v in = +3.0v, shdn = in, v supp = v supn = v supb = v supl = 10v, ldoout = fbl, buf- = bufout, buf+ = fltset = tgnd = pgnd = gnd, c ref = 0.22f, c buf = 1f, t a = 0 c to +85 c . typical values are at t a = +25 c, unless otherwise noted.) parameter symbol conditions min typ max units negative charge pump (max1778/max1880/max1881/max1882 only) supn input supply range v supn 2.7 13 v operating frequency f chp 0.5 x f osc hz fbn regulation voltage v fbn -50 0 +50 mv fbn input bias current i fbn v fbn = 0 -50 +50 na drvn pch on-resistance r pch ( on ) 510 ? v fbn = +50mv 24 ? drvn nch on-resistance r nch ( on ) v fbn = -50mv 20 k ? maximum rms drvn current 0.1 a fbn power-ready trip level falling edge 80 125 165 mv fbn fault trip level rising edge 80 140 190 mv low-dropout linear regulator (max1778/max1881/max1883/max1884 only) supl input supply range v supl 4.5 15 v supl undervoltage lockout rising edge, 50mv hysteresis (typ) 3.8 4 4.3 v supl quiescent current i supl i ldo = 100a 120 220 a i ldo = 40ma 130 300 dropout voltage (note 1) v drop ldo is set to regulate at 9v i ldo = 5ma 70 mv fbl regulation voltage v fbl v supl = 10v, ldo regulating at 9v, i ldo = 15ma 1.235 1.25 1.265 v ldo load regulation v supl = 10v, ldo regulating at 9v, i ldo = 100a to 40ma 1.2 % ldo line regulation v supl = 4.5v to 15v, fbl = ldoout, i ldo = 15ma 0.02 %/v fbl input bias current i fbl v fbl = 1.25v -0.8 +0.8 a ldo current limit i ldolim v supl = 10v, v ldoout = 9v, v fbl = 1.2v 40 130 220 ma vcom buffer supb input supply range v supb 4.5 13 v supb quiescent current i supb v supb = 13v 420 850 a bufout leakage current -10 +10 a power-supply rejection ratio psrr v supb = 4.5v to 13v, v cm = 2.25v 85 98 db input common-mode voltage range v cm |v os | < 10mv 1.2 8.8 v common-mode rejection ratio cmrr v cm = 1.2v to 8.8v 75 db input bias current i bias v cm = 5v -100 -10 +100 na input offset current i os v cm = 5v -100 +100 na gain bandwidth product gbw c buf = 1f 13 khz
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer _______________________________________________________________________________________ 5 electrical characteristics (continued) (v in = +3.0v, shdn = in, v supp = v supn = v supb = v supl = 10v, ldoout = fbl, buf- = bufout, buf+ = fltset = tgnd = pgnd = gnd, c ref = 0.22f, c buf = 1f, t a = 0 c to +85 c . typical values are at t a = +25 c, unless otherwise noted.) parameter symbol conditions min typ max units i bufout = 0 4.99 5.01 i bufout = 5ma 4.97 5.03 v output voltage v bufout buf+ = gnd i bufout = 45ma 4.93 5.07 i bufout = 5ma -30 30 input offset voltage v os v supb = 4.5v to 13v, v cm = 1.2v to (v supb 1.2v) i bufout = 45ma -70 70 mv output voltage swing high v oh i bufout = -45ma, ? v os = 1v 9 9.6 v output voltage swing low v ol i bufout = +45ma, ? v os = 1v 0.4 1 v peak buffer output current 150 ma buf+ dual mode threshold voltage falling edge, 20mv hysteresis (typ) 80 125 170 mv reference reference voltage v ref -2 a < i ref < 50a 1.231 1.25 1.269 v reference undervoltage threshold 0.9 1.05 1.2 v logic signals shdn input low voltage 0.9 v shdn input high voltage 2.1 v shdn input current i shdn 0.01 1 a fltset input voltage range 0.67 x v ref 0.85 x v ref v fltset threshold voltage rising edge, 25mv hysteresis (typ) 80 125 170 mv fltset input current v fltset = 1v 0.1 50 na rdy output low voltage i sink = 2ma 0.25 0.5 v rdy output high leakage v rdy = 13v 0.01 1 a thermal shutdown rising temperature 160 c dual mode is a registered trademark of maxim integrated products, inc.
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer 6 _______________________________________________________________________________________ electrical characteristics (v in = +3.0v, shdn = in, v supp = v supn = v supb = v supl = 10v, ldoout = fbl, buf- = bufout, buf+ = fltset = tgnd = pgnd = gnd, c ref = 0.22f, c buf = 1f, t a = -40 c to +85 c , unless otherwise noted.) (note 2) parameter symbol conditions min max units input supply range v in 2.7 5.5 v input undervoltage threshold v uvlo v in rising, 40mv hysteresis (typ) 2.2 2.6 v max1778/max1880/ max1883 (f osc = 1mhz) 1 in quiescent supply current i in v fb = v fbp = 1.5v, v fbn = -0.2v max1881/max1882/max1884/ max1885 (f osc = 500khz) 1 ma max1778/max1880 (f osc = 1mhz) 0.7 supp quiescent current i supp v fbp = 1.5v max1881/max1882 (f osc = 500khz) 0.5 ma max1778/max1880 (f osc = 1mhz) 0.7 supn quiescent current i supn v fbn = -0.2v max1881/max1882 (f osc = 500khz) 0.5 ma in shutdown current v shdn = 0, v in = 5v 10 a supp shutdown current v shdn = 0, v supp = 13v, max1778/max1880/max1881/max1882 10 a supn shutdown current v shdn = 0, v supn = 13v, max1778/max1880/max1881/max1882 10 a supl shutdown current v shdn = 0, v supl = 13v, max1778/max1881/max1883/max1884 10 a supb shutdown current v shdn = 0, v supb = 13v 13 a main step-up converter main output voltage range v main v in 13 v integrator enabled, c intg = 1000pf 1.223 1.269 fb regulation voltage v fb integrator disabled (intg = ref) 1.21 1.29 v fb input bias current i fb v fb = 1.25v, intg = gnd -50 +50 na max1778/max1880/max1883 0.75 1.25 mhz operating frequency f osc max1881/max1882/max1884/max1885 375 625 khz oscillator maximum duty cycle 79 91 % lx switch on-resistance r lx ( on ) i lx = 100ma 0.7 ? lx leakage current i lx v lx = 13v 20 a phase i = soft-start (1024/f osc ) 0.275 0.525 lx current limit i lim phase iv = fully on (after 3072/f osc ) 1.1 2.05 a fb fault trip level falling edge, fltset = gnd 1.07 1.14 v
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer _______________________________________________________________________________________ 7 electrical characteristics (continued) (v in = +3.0v, shdn = in, v supp = v supn = v supb = v supl = 10v, ldoout = fbl, buf- = bufout, buf+ = fltset = tgnd = pgnd = gnd, c ref = 0.22f, c buf = 1f, t a = -40 c to +85 c , unless otherwise noted.) (note 2) parameter symbol conditions min max units positive charge pump (max1778/max1880/max1881/max1882 only) supp input supply range v supp 2.7 13 v fbp regulation voltage v fbp 1.2 1.3 v fbp input bias current i fbp v fbp = 1.5v -50 +50 na drvp pch on-resistance r pch ( on ) 10 ? v fbp = 1.2v 4 ? drvp nch on-resistance r nch ( on ) v fbp = 1.3v 20 k ? fbp power-ready trip level rising edge 1.09 1.16 v negative charge pump (max1778/max1880/max1881/max1882 only) supn input supply range v supn 2.7 13 v fbn regulation voltage v fbn -50 +50 mv fbn input bias current i fbn v fbn = 0 -50 +50 na drvn pch on-resistance r pch ( on ) 10 ? v fbn = +50mv 4 ? drvn nch on-resistance r nch ( on ) v fbn = -50mv 20 k ? fbn power-ready trip level falling edge 80 165 mv low dropout linear regulator (max1778/max1881/max1883/max1884 only) supl input supply range v supl 4.5 15 v supl undervoltage lockout rising edge, 50mv hysteresis (typ) 3.8 4.3 v supl quiescent current i supl i ldo = 100a 240 a dropout voltage (note 1) v drop ldo regulating to 9v, i ldo = 40ma 330 mv fbl regulation voltage v fbl v supl = 10v, ldo regulating to 9v, i ldo = 15ma 1.222 1.265 v ldo load regulation v supl = 10v, ldo regulating to 9v, i ldo = 100a to 40ma 1.2 % ldo line regulation v supl = 4.5v to 15v, fbl = ldoout, i ldo = 15ma 0.02 %/v fbl input bias current i fbl v fbl = 1.25v -1.2 +1.2 a ldo current limit i ldolim v supl = 10v, v ldoout = 9v, v fbl = 1.2v 40 260 ma vcom buffer supb input supply range v supb 4.5 13 v supb quiescent current i supb v supb = 13v 850 a bufout leakage current -10 +10 a input common-mode voltage v cm |v os | < 10mv 1.2 8.8 v
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer 8 _______________________________________________________________________________________ electrical characteristics (continued) (v in = +3.0v, shdn = in, v supp = v supn = v supb = v supl = 10v, ldoout = fbl, buf- = bufout, buf+ = fltset = tgnd = pgnd = gnd, c ref = 0.22f, c buf = 1f, t a = -40 c to +85 c , unless otherwise noted.) (note 2) parameter symbol conditions min max units input bias current i bias v cm = 5v -500 +500 na input offset current i os v cm = 5v -500 +500 na i bufout = 0 4.988 5.012 i bufout = 5ma 4.97 5.03 output voltage v bufout buf+ = gnd i bufout = 45ma 4.93 5.07 v i bufout = 5ma -30 30 input offset voltage v os v supb = 4.5v to 13v v cm = 1.2v to (v supb - 1.2v) i bufout = 45ma -70 70 mv output voltage swing high v oh i bufout = -45ma, ? v os = 1v 9 v output voltage swing low v ol i bufout = +45ma, ? v os = 1v 1 v buf+ dual mode threshold voltage falling edge, 20mv hysteresis (typ) 80 170 mv reference reference voltage v ref -2a < i ref < 50a 1.223 1.269 v reference undervoltage threshold 0.9 1.2 v logic signals shdn input low voltage 0.9 v shdn input high voltage 2.1 v shdn input current i shdn 1a fltset input voltage range 0.74 x v ref 0.85 x v ref v fltset threshold voltage rising edge, 25mv hysteresis (typ) 80 170 mv fltset input current v fltset = 1v 50 na rdy output low voltage i sink = 2ma 0.5 v rdy output high leakage v rdy = 13v 1 a note 1: dropout voltage is defined as the v supl - v ldoout , when v supl is 100mv below the set value of v ldoout . note 2: specifications to -40 c are guaranteed by design, not production tested.
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer _______________________________________________________________________________________ 9 7.88 7.92 7.96 8.00 8.04 8.08 8.12 0 200 400 600 800 main 8v output voltage vs. load current max1778 toc01 i out (ma) v out (v) v in = 5v r comp = 24k ? c comp = 470pf v in = 3.3v c intg = 470pf 40 50 60 70 80 90 100 0 200 400 600 800 main 8v output efficiency vs. load current max1778 toc02 i out (ma) efficiency (%) v in = 3.3v v out = 8v r comp = 24k ? c comp = 470pf c intg = 470pf v in = 5v 11.76 11.92 11.84 12.08 12.00 12.16 12.24 0 200 300 100 400 500 600 main 12v output voltage vs. load current max1778 toc03 i out (ma) v out (v) figure 8 c intg = 470pf v in = 3.3v v in = 5v 40 60 50 80 70 90 100 0 200 300 100 400 500 600 main 12v output efficiency vs. load current max1778 toc04 i out (ma) efficiency (%) figure 8 v out = 12v c intg = 470pf v in = 3.3v v in = 5v 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 2.5 3.5 3.0 4.0 4.5 5.0 5.5 step up converters switching frequency vs. input voltage max1778 toc05 v in (v) switching frequency (mhz) max1778 19.2 19.4 19.8 19.6 20.0 20.2 positive charge-pump output voltage vs. load current max1778 toc06 i pos (ma) v pos (v) 010 51520 v supp = 10v v supp = 8v v supp = 7.5v v supp = 7v 30 80 70 90 100 positive charge-pump efficiency vs. load current max1778 toc07 i neg (ma) efficiency (%) 010 51520 v pos = 20v v supp = 7.5v v supp = 7v v supp = 8v v supp = 10v 60 50 40 5 15 10 25 20 35 30 40 268 4 101214 maximum positive charge-pump output voltage vs. supply voltage max1778 toc08 v supp (v) v pos (v) i pos = 10ma i pos = 1ma -5.04 -5.00 -5.02 -4.96 -4.98 -4.92 -4.94 -4.90 negative charge-pump output voltage vs. load current max1778 toc09 i neg (ma) v neg (v) 0 10203040 v supn = 7v v supn = 8v v supn = 6v typical operating characteristics (circuit of figure 1, v in = +3.3v, shdn = in, v main = v supp = v supn = v supb = v supl = 8v, buf- = bufout, buf+ = fltset = tgnd = pgnd = gnd, t a = +25 c.)
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer 10 ______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 1, v in = +3.3v, shdn = in, v main = v supp = v supn = v supb = v supl = 8v, buf- = bufout, buf+ = fltset = tgnd = pgnd = gnd, t a = +25 c.) 30 50 40 70 60 90 80 100 negative charge-pump efficiency vs. load current max1778 toc10 i neg (ma) efficiency (%) 0 10203040 v supn = 7v v supn = 8v v supn = 6v v neg = -5v -14 -10 -12 -6 -8 -4 -2 268 4 101214 maximum negative charge-pump output voltage vs. supply voltage max1778 toc11 v supn (v) v neg (v) i neg = 10ma i neg = 1ma 1.23 1.24 1.25 1.26 1.27 0 20406080100 reference voltage vs. reference load current max1778 toc12 i ref ( a) v ref (v) step-up converter load-transient response max1778 toc13 200ma 0 8.1v 8.0v 7.9v 1a 0 40 s/div a. i main = 20ma to 200ma, 200ma/div b. v main = 8v, 100mv/div c. inductor current, 1a/div c intg = 1000pf c b a step-up converter load-transient response without integrator max1778 toc14 200ma 0 8.1v 8.0v 7.9v 1a 0 40 s/div a. i main = 20ma to 200ma, 200ma/div b. v main = 8v, 100mv/div c. inductor current, 1a/div intg = ref c b a step-up converter load-transient response (1 s pulses) max1778 toc15 0.5a 0 8.0v 7.9v 1a 0.5a 0 4 s/div a. i main = 0 to 500ma, 500ma/div b. v main = 8v, 100mv/div c. inductor current, 500ma/div c b a
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer ______________________________________________________________________________________ 11 ripple voltage waveforms max1778 toc16 8v -5v 20v 1 s/div a. v main = 8v, i main = 200ma, 10mv/div b. v neg = -5v, i neg = 10ma, 20mv/div c. v pos = 20v, i pos = 5ma, 20mv/div c b a step-up converter soft-start (light load) max1778 toc17 0 6v 0.5a 1ms/div a. v shdn = o to 2v, 2v/div b. v main = 8v, 2v/div c. inductor current, 500ma/div r load = 400 ? c b a 2v 8v 4v 0 step-up converter soft-start (heavy load) max1778 toc18 0 6v 1.0a 1ms/div a. v shdn = o to 2v, 2v/div b. v main = 8v, 2v/div c. inductor current, 500ma/div r load = 20 ? c b a 2v 8v 4v 0.5a 0 power-up sequence max1778 toc19 0 0 10v 2ms/div a. v shdn = o to 2v, 2v/div b. rdy, 5v/div c. positive charge pump = v pos = 20v, r load = 4k ? , 10v/div d. step-up converter: v main = 8v, r load = 40 ? , 10v/div e. negative charge pump: v neg = -5v, r load = 500 ? , 10v/div e b a 2v 5v 20v 0 -10v c d power-up sequence (circuit of fig.10) max1778 toc20 0 10v 0 1ms/div a. rdy, 2v/div b. positive charge pump, v pos(sys) = 20v, 10v/div c. step-up converter: v main(sys) = 8v, 10v/div d. negative charge pump, v neg = -5v, -5v/div b a 2v 20v 0 -5v c d 4v max1778 toc21 c b a 10v 5v 4v 5v 2v 0 0 0 100 s/div power-up into short-circuit (circuit of fig. 10) a. rdy, 2v/div b. gate of n-ch mosfet, 5v/div c. step-up converter, v main(start) = 8v, 5v/div v main(sys) = gnd typical operating characteristics (continued) (circuit of figure 1, v in = +3.3v, shdn = in, v main = v supp = v supn = v supb = v supl = 8v, buf- = bufout, buf+ = fltset = tgnd = pgnd = gnd, t a = +25 c.)
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer 12 ______________________________________________________________________________________ 4.75 4.80 4.85 4.90 4.95 5.00 5.05 max1778 toc22 v supl (v) v ldoout (v) ldo output voltage vs. ldo input voltage (internal linear regulator) 48 61012 i ldoout = 0 i ldoout = 40ma 5.04 5.02 4.90 0.01 0.1 10 100 4.92 4.96 4.94 5.00 4.98 max1778 toc23 i ldoout (ma) v ldoout (v) 1 ldo output voltage vs. ldo output current (internal linear regulator) 4.90 4.96 4.94 4.92 4.98 5.00 5.02 5.04 5.06 5.08 5.10 -40 10 -15 35 60 85 ldo output voltage vs. temperature (internal linear regulator) max1778 toc24 temperature ( c) v ldo (v) i ldoout = 0 i ldoout = 40ma 0 40 120 80 160 200 max1778 toc25 i ldoout (ma) v supl - v ldoout (mv) 020 10 30 40 dropout voltage vs. ldo load current (internal linear regulator) v ldoout = 5v 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 10203040 max1778 toc26 i ldoout (ma) i supl - i ldoout (ma) ldo supply current vs. ldo output current (internal linear regulator) v ldoout = 5v typical operating characteristics (continued) (circuit of figure 1, v in = +3.3v, shdn = in, v main = v supp = v supn = v supb = v supl = 8v, buf- = bufout, buf+ = fltset = tgnd = pgnd = gnd, t a = +25 c.)
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer ______________________________________________________________________________________ 13 0 11000 100 10 100 40 20 80 60 max1778 toc27 frequency (khz) psrr (db) power-supply rejection ratio vs. frequency c ldoout = 4.7 f i ldoout = 40ma 040 region of stable c ldoout esr vs. load current max1778 toc28 i ldoout (ma) c ldoout esr ( ? ) 10 20 30 100 0.01 0.1 10 1 c ldoout = 1 f stable region max1778 toc29 b a 4.96v 4oma 0 5.00v 100 s/div load-transient response (internal linear regulator) a. i ldo = 100 a to 40ma, 40ma/div b. v ldo = 5v, 20mv/div v supl = v ldo + 500mv max1778 toc30 b a 4.94v 4oma 0 5.00v 100 s/div load-transient response near dropout (internal linear regulator) a. i ldo = 100 a to 40ma, 40ma/div b. v ldo = 5v, 20mv/div v in = v ldo + 100mv max1778 toc31 c b a 0.5a 0 5.0v 8.0v 1.0a 10 s/div internal linear-regulator ripple rejection a. v ldoout = 5v, i ldoout = 40ma, 10mv/div b. v main = v supl = 8v, 200mv/div c. i main = 0 to 750ma, 500ma/div max1778 toc32 c b a 4v 2v 2v 0 2v 4v 0 400 s/div internal linear-regulator startup a. v s hdn = 0 to 2v, 2v/div b. v ldoout = 5v, r ldoout = 125 ? , 2v/div c. v main = 8v, r main = 40 ? , 2v/div typical operating characteristics (continued) (circuit of figure 1, v in = +3.3v, shdn = in, v main = v supp = v supn = v supb = v supl = 8v, buf- = bufout, buf+ = fltset = tgnd = pgnd = gnd, t a = +25 c.)
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer 14 ______________________________________________________________________________________ 2.45 2.47 2.49 2.51 2.53 2.55 2.5 3.5 3.0 4.0 4.5 5.0 5.5 max1778 toc33 v in (v) v ldo (v) linear-regulator output voltage vs. input voltage (external linear regulator) i ldo = 0 i ldo = 750ma figure 7 2.55 2.45 0.1 1 10 100 1000 2.47 max1778 toc34 i ldo (ma) v ldo (v) 2.49 2.51 2.53 linear-regulator output voltage vs. load current (external linear regulator) figure 7 max1778 toc35 b a 2.45v 250ma 2.55v 50ma 2.50v 100 s/div external linear-regulator load-transient response a. i ldo = 50ma to 250ma, 200ma/div b. v ldo = 2.5v, 50mv/div figure 7 max1778 toc36 c b a 0.5a 0 2.5v 7.8v 8.0v 1a 10 s/div external linear-regulator ripple rejection a. v ldo = 2.5v, i ldo = 200ma, 10mv/div b. v main = v supl = 8v, 200mv/div c. i main = 0 to 750ma, 500ma/div figure 7 -2.5 -1.5 -0.5 1.5 0.5 2.5 02468101214 max1778 toc37 v cm (v) ? v os (mv) input offset voltage deviation vs. common-mode voltage v supb = 4.5v v supb = 13v -1.0 -0.6 -0.2 0.2 0.6 1.0 48 6101214 max1778 toc38 v supb (v) ? v os (mv) input offset voltage deviation vs. buffer supply voltage v cm = v supb / 2 typical operating characteristics (continued) (circuit of figure 1, v in = +3.3v, shdn = in, v main = v supp = v supn = v supb = v supl = 8v, buf- = bufout, buf+ = fltset = tgnd = pgnd = gnd, t a = +25 c.)
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer ______________________________________________________________________________________ 15 0 -0.6 -0.2 0.2 0.6 1.0 -40 10 -15 35 60 85 max1778 toc39 temperature ( c) ? v os (mv) input offset voltage deviation vs. temperature v supb = 13v v cm = v supb / 2 0 -0.6 -0.2 0.2 0.6 1.0 -40 10 -15 35 60 85 max1778 toc39 temperature ( c) ? v os (mv) input offset voltage deviation vs. temperature v supb = 13v v cm = v supb / 2 0 2 6 4 8 10 04 2 6 8 101214 max1778 toc41 v cm (v) i bias (na) buffer input bias current vs. common-mode voltage v supb = 4.5v v supb = 13v 4 6 8 10 48 6 101214 max1778 toc42 v supb (v) i bias (na) buffer input bias current vs. buffer supply voltage v cm = v supb / 2 4 5 6 7 8 9 10 11 12 -40 -15 10 35 60 85 max1778 toc43 temperature ( c) i bias (na) buffer input bias current vs. temperature v cm = v supb / 2 0.30 0.34 0.42 0.38 0.46 0.50 04 2 6 8 101214 max1778 toc44 v cm (v) i supb (ma) buffer supply current vs. common-mode voltage v supb = 4.5v v supb = 13v 0.30 0.34 0.38 0.42 0.46 0.50 48 6101214 max1778 toc45 v supb (v) i supb (ma) buffer supply current vs. buffer supply voltage v cm = v supb / 2 0 0.3 0.2 0.1 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -40 10 -15 35 60 85 i supb (ma) max1778 toc46 temperature ( c) no-load buffer supply current vs. temperature v supb = 13v v cm = v supb / 2 max1778 toc47 b a 4.00v 3.95v 4.05v 4.00v 3.95v 4.05v 4 s/div vcom buffer small-signal response a. v buf+ = 3.95v to 4.05v, 50mv/div b. bufout = buf-, 50mv/div c buf = 1 f, v supb = 8v typical operating characteristics (continued) (circuit of figure 1, v in = +3.3v, shdn = in, v main = v supp = v supn = v supb = v supl = 8v, buf- = bufout, buf+ = fltset = tgnd = pgnd = gnd, t a = +25 c.)
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer 16 ______________________________________________________________________________________ max1778 toc48 b a 4.00v 3.50v 4.50v 4.00v 3.50v 4.50v 10 s/div vcom buffer large-signal response a. v buf + = 3.50v to 4.50v, 0.5v/div b. bufout = buf-, 0.5v/div c buf = 1 f, v supb = 8v max1778 toc49 c b a 3.8v 8.0v 200ma 4.2v 0 -200ma 4.0v 4 s/div vcom buffer load-transient response a. i bufout = 200ma pulses, 200ma/div b. bufout = buf-, 200mv/div c. v main = 8v, 50mv/div v supb = v main , buf+ = gnd, c buf = 1 f max1778 toc50 c b a 3.5v 8.0v 500ma 4.5v 0 -500ma 4.0v 4 s/div vcom buffer load-transient response a. i bufout = 400ma pulses, 500ma/div b. bufout = buf-, 0.5v/div c. v main = 8v, 100mv/div v supb = v main , buf+ = gnd, c buf = 1 f typical operating characteristics (continued) (circuit of figure 1, v in = +3.3v, shdn = in, v main = v supp = v supn = v supb = v supl = 8v, buf- = bufout, buf+ = fltset = tgnd = pgnd = gnd, t a = +25 c.) max1778 toc51 c b a 8.1v 7.8v 2v 4v 2v 0 4v 0 100 s/div vcom buffer startup a. rdy, 2v/div b. bufout = buf-, c buf = 1 f, 2v/div c. v supb = v main = 8v, i main = 20ma, 200mv/div buf+ = gnd max1778 toc51 c b a 8.1v 7.8v 2v 4v 2v 0 4v 0 100 s/div vcom buffer startup a. rdy, 2v/div b. bufout = buf-, c buf = 1 f, 2v/div c. v supb = v main = 8v, i main = 20ma, 200mv/div buf+ = gnd
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer ______________________________________________________________________________________ 17 pin description pin max1778 max1881 max1880 max1882 max1883 max1884 max1885 name function 1111fb main step-up regulator feedback input. regulates to 1.25v nominal. connect a resistive divider from the output (v main ) to fb to analog ground (gnd). 2222intg main step-up integrator output. when using the integrator, connect 1000pf to analog ground (gnd). to disable the integrator, connect intg to ref. 3333in main supply voltage. the supply voltage powers the control circuitry for all of the regulators and may range from 2.7v to 5.5v. bypass with a 0.1f capacitor between in and gnd, as close to the pins as possible. 4444 buf+ vcom buffer (operational transconductance amplifier) positive feedback input. connect to gnd to select the internal resistive divider that sets the positive input to half the amplifier s supply voltage (v buf+ = v supb /2). 5555 buf- vcom buffer (operational transconductance amplifier) negative feedback input 6666 supb vcom buffer (operational transconductance amplifier) supply voltage 7777 bufout vcom buffer (operational transconductance amplifier) output 8888gnd analog ground. connect to power ground (pgnd) underneath the ic. 9999ref internal reference bypass terminal. connect a 0.22f ceramic capacitor from ref to analog ground (gnd). external load capability up to 50a. 10 10 ?? fbp positive charge-pump regulator feedback input. regulates to 1.25v nominal. connect a resistive divider from the positive charge-pump output (v pos ) to fbp to analog ground (gnd). 11 11 ?? fbn negative charge-pump regulator feedback input. regulates to 0v nominal. connect a resistive divider from the negative charge- pump output (v neg ) to fbn to the reference (ref). 12 12 10 10 shdn active-low shutdown control input. pull shdn low to force the controller into shutdown. if unused, connect shdn to in for normal operation. a rising edge on shdn clears the fault latch. 13 ? 11 ? supl low-dropout linear regulator input voltage. can range from 4.5v to 15v. bypass with a 1f capacitor to gnd (see capacitor selection and regulator stability ). connect both input pins together externally.
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer 18 ______________________________________________________________________________________ pin description (continued) pin max1778 max1881 max1880 max1882 max1883 max1884 max1885 name function 14 ? 12 ? ldoout linear regulator output. sources up to 40ma. bypass to gnd with a ceramic capacitor determined by: 15 ? 13 ? fbl voltage setting input. connect a resistive divider from the linear regulator output (v ldoout ) to fbl to analog ground (gnd). 16 16 14 14 fltset fault trip-level set input. connect to a resistive divider between ref and gnd to set the main step-up converter s and positive charge pump s fault thresholds between 0.67 x v ref and 0.85 x v ref . connect to gnd for the preset fault threshold (0.9 x v ref ). 17 17 ?? supn negative charge-pump driver supply voltage. bypass to power ground (pgnd) with a 0.1f capacitor. 18 18 ?? drvn negative charge-pump driver output. output high level is v supn and low level is pgnd. 19 19 ?? supp positive charge-pump driver supply voltage. bypass to power ground (pgnd) with a 0.1f capacitor. 20 20 ?? drvp positive charge-pump driver output. output high level is v supp and low level is pgnd 21 21 17 17 pgnd power ground. connect to analog ground (gnd) underneath the ic. 22 22 18 18 lx main step-up regulator power mosfet n-channel drain. place output diode and output capacitor as close to pgnd as possible. 23 23 19 19 tgnd must be connected to ground. 24 24 20 20 rdy active-low, open-drain output. indicates all outputs are ready. on-resistance is 125 ? (typ). ? 13, 14, 15 15, 16 11, 12, 13, 15, 16 n.c. no connection. not internally connected. cmsx i v ldoout ldoout max ldoout . () ? ? ? ? ? ? 05
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer ______________________________________________________________________________________ 19 detailed description the max1778/max1880 max1885 are highly efficient multiple-output power supplies for thin-film transistor (tft) liquid crystal display (lcd) applications. the devices contain one high-power step-up converter, two low-power charge pumps, an operational transconduc- tance amplifier (v com buffer), and a low-dropout linear regulator. the primary step-up converter uses an inter- nal n-channel mosfet to provide maximum efficiency and to minimize the number of external components. the output voltage of the main step-up converter (v main ) can be set from v in to 13v with external resis- tors. the dual charge pumps (max1778/max1880/ max1881/max1882 only) independently regulate a positive output (v pos ) and a negative output (v neg ). these low-power outputs use external diode and capacitor stages (as many stages as required) to regu- late output voltages from -40v to +40v. a unique control scheme minimizes output ripple as well as capacitor sizes for both charge pumps. a resistor-programmable 40ma linear regulator (max1778/max1881/max1883/max1884 only) can provide preregulation or postregulation for any of the supplies. for higher current applications, an external transistor can be added. additionally, the v com buffer provides a high current output that is ideal for driving capacitive loads, such as the backplane of a tft lcd panel. the positive feed- back input features dual mode operation, allowing this input to be connected to an internal 50% resistive- divider between the buffer s supply voltage and ground, or externally adjusted for other voltages. also included in the max1778/max1880 max1885 is a precision 1.25v reference that sources up to 50a, logic shutdown, soft-start, power-up sequencing, adjustable fault detection, thermal shutdown, and an active-low, open-drain ready output. in buffer output v bufout = v supb /2 positive v pos = 20v c buf 1.0 f c ldo 4.7 f c ref 0.22 f c7 1.0 f c5 1.0 f c4 0.1 f l1 6.8 h c4 0.1 f c2 0.1 f c1 0.22 f c in 4.7 f shdn rdy supl ldoout supn supp drvp fbp r3 750k ? r5 200k ? r7 150k ? r4 49.9k ? r6 49.9k ? r8 49.9k ? r2 49.9k ? r2 274k ? lx input v in = 3.3v ldo v ldoout = 5v negative v neg = -5v to logic fb bufout buf- buf+ gnd tgnd fbl drvn fbn ref fltset intg pgnd supb max1778 main v main = 8v main (8v) c out (2) 4.7 f c3 1.0 f r rdy 100k ? figure 1. typical application circuit
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer 20 ______________________________________________________________________________________ main step-up controller during normal pulse-width modulation (pwm) opera- tion, the max1778/max1880 max1885 main step-up controllers switch at a constant frequency of 500khz or 1mhz (see selector guide ), allowing the use of low- profile inductors and output capacitors. depending on the input-to-output voltage ratio, the controller regulates the output voltage and controls the power transfer by modulating the duty cycle (d) of each switching cycle: on the rising edge of the internal clock, the controller sets a flip-flop when the output voltage is too low, which turns on the n-channel mosfet (figure 2). the induc- tor current ramps up linearly, storing energy in a mag- netic field. once the sum of the feedback voltage error amplifier, slope-compensation, and current-feedback signals trip the multi-input comparator, the mosfet turns off, the flip-flop resets, and the diode (d1) turns on. this forces the current through the inductor to ramp back down, transferring the energy stored in the mag- netic field to the output capacitor and load. the mos- fet remains off for the rest of the clock cycle. changes in the feedback voltage-error signal shift the switch-cur- rent trip level, consequently modulating the mosfet duty cycle. under very light loads, an inherent switchover to pulse- skipping takes place (figure 3). when this occurs, the controller skips most of the oscillator pulses in order to reduce the switching frequency and gate charge loss- es. when pulse-skipping, the step-up controller initiates a new switching cycle only when the output voltage drops too low. the n-channel mosfet turns on, allow- ing the inductor current to ramp up until the multi-input comparator trips. then, the mosfet turns off and the diode turns on, forcing the inductor current to ramp down. when the inductor current reaches zero, the diode turns off, so the inductor stops conducting cur- rent. this forces the threshold between pulse-skipping and pwm operation to coincide with the boundary between continuous and discontinuous inductor-cur- rent operation: i v v vv fl load crossover in main main in osc () ? ? ? ? ? ? ? ? ? ? ? ? 1 2 2 - d vv v main in main - max1778 max1880 max1881 max1882 max1883 max1884 max1885 v main = 1 + v ref v ref = 1.25v r1 r2 ( ) s r i lim q c ref v ref 1.25v g m l1 d1 r1 r2 intg c intg r comp (optional) c comp (optional) c in c out v main (up to 13v) v in (2.7v to 5.5v) osc (80% duty) ref gnd lx fb pgnd pwm comparator error amplifier ilim comparator figure 2. main step-up converter block diagram
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer ______________________________________________________________________________________ 21 the switching waveforms will appear noisy and asyn- chronous when light loading causes pulse-skipping operation; this is a normal operating condition that improves light-load efficiency. dual charge-pump regulator (max1778/ max1880/max1881/max1882 only) the max1778/max1880/max1881/max1882 con- trollers contain two independent low-power charge pumps (figure 4). one charge pump inverts the input voltage and provides a regulated negative output volt- age. the second charge pump doubles the input volt- age and provides a regulated positive output voltage. the controllers contain internal p-channel and n-chan- nel mosfets to control the power transfer. the internal mosfets switch at a constant frequency (fchp = fosc/2). positive charge pump during the first half-cycle, the n-channel mosfet turns on and charges flying capacitor c x(pos) (figure 4). this initial charge is controlled by the variable n-chan- nel on-resistance. during the second half-cycle, the n- channel mosfet turns off and the p-channel mosfet turns on, level shifting c x(pos) by v supp volts. this connects c x(pos) in parallel with the reservoir capaci- tor c out(pos) . if the voltage across c out(pos) plus a diode drop (v pos + v diode ) is smaller than the level- shifted flying capacitor voltage (v cx(pos) + v supp ), charge flows from c x(pos) to c out(pos) until the diode (d3) turns off. inductor current i load t on t off time i peak figure 3. discontinuous-to-continuous conduction crossover point max1778 max1880 max1881 max1882 v neg = - v ref v ref = 1.25v ( ) r5 r6 r5 r6 c out(neg) c x(neg) v supn 2.7v to 13v osc ref pgnd gnd supn drvn fbn supp drvp fbp d4 d5 v pos = 1 + v ref v ref = 1.25v r3 r4 ( ) v supp 2.7v to 13v v supd d2 d3 c ref 0.22 f v ref 1.25v r4 c x(pos) c out(pos) v pos v neg r3 figure 4. low-power charge pump block diagram
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer 22 ______________________________________________________________________________________ negative charge pump during the first half-cycle, the p-channel mosfet turns on, and flying capacitor c x(neg) charges to v supn minus a diode drop (figure 4). during the second half- cycle, the p-channel mosfet turns off, and the n- channel mosfet turns on, level shifting c x(neg) . this connects c x(neg) in parallel with reservoir capacitor c out(neg) . if the voltage across c out(neg) minus a diode drop is greater than the voltage across c x(neg) , charge flows from c out(neg) to c x(neg) until the diode (d5) turns off. the amount of charge transferred to the output is controlled by the variable n-channel on-resis- tance. low-dropout linear regulator (max1778/ max1881/max1883/max1884 only) the max1778/max1881/max1883/max1884 contain a low-dropout linear regulator (figure 5) that uses an internal pnp pass transistor (q p ) to supply loads up to 40ma. as illustrated in figure 5, the 1.25v reference is connected to the error amplifier, which compares this reference with the feedback voltage and amplifies the difference. if the feedback voltage is higher than the reference voltage, the controller lowers the base cur- rent of q p , which reduces the amount of current to the output. if the feedback voltage is too low, the device increases the pass transistor base current, which allows more current to pass to the output and increases the output voltage. however, the linear regulator also includes an output current limit to protect the internal pass transistor against short circuits. the low-dropout linear regulator monitors and controls the pass transistor s base current, limiting the output current to 130ma (typ). in conjunction with the thermal overload protection, this current limit protects the out- put, allowing it to be shorted to ground for an indefinite period of time without damaging the part. vcom buffer the max1778/max1880 max1885 include a vcom buffer, which uses an operational transconductance amplifier (ota) to provide a current output that is ideal for driving capacitive loads, such as the backplane of a tft lcd panel. the unity-gain bandwidth of this cur- rent-output buffer is: gbw = gm/c out where gm is the amplifier s transconductance. the bandwidth is inversely proportional to the output capacitor, so large capacitive loads improve stability; however, lower bandwidth decreases the buffer s tran- sient response time. to improve the transient response supl c supl v supl 4.5v to 15v c ldoout ldoout v ldoout 1.25v to (v supl - 0.3v) fbl v ref 1.25v error amplifier gnd r8 r7 q p current limit thermal sensor v ldoout = ( 1 + ) v ref v ref = 1.25v r7 r8 max1778 max1881 max1883 max1884 figure 5. low-dropout linear regulator block diagram
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer ______________________________________________________________________________________ 23 times, the amplifier s transconductance increases as the output current increases (see typical operating characteristics ). the vcom buffer s positive feedback input features dual mode operation. the buffer s output voltage can be internally set by a 50% resistive divider connected to the buffer s supply voltage (supb), or the output volt- age can be externally adjusted for other voltages. shutdown (shdn) a logic-low level on shdn shuts down all of the con- verters and the reference. when shut down, the supply current drops to 0.1a to maximize battery life, and the reference is pulled to ground. the output capacitance, feedback resistors, and load current determine the rate at which each output voltage will decay. a logic-level high on shdn power activates the max1778/ max1880 max1885 (see power-up sequencing). do not leave shdn floating. if unused, connect shdn to in. a logic-level transition on shdn clears the fault latch. power-up sequencing upon power-up or exiting shutdown, the max1778/ max1880 max1885 start a power-up sequence. first, the reference powers up. then, the main dc-dc step- up converter powers up with soft-start enabled. the lin- ear regulator powers up at the same time as the main step-up converter; however, the power sequence and ready output signal are not affected by the regulation of the linear regulator. while the main step-up converter powers up, the output of the pwm comparator remains low (figure 2), and the step-up converter charges the output capacitors, limited only by the maximum duty cycle and current-limit comparator. when the step-up converter approaches its nominal regulation value and the pwm comparator s output changes states for the first time, the negative charge pump turns on. when the negative output voltage reaches approximately 90% of its nominal value (v fbn < 110mv), the positive charge pump starts up. finally, when the positive output volt- age reaches 90% of its nominal value (v fbp > 1.125v), the active-low ready signal ( rdy ) goes low (see power ready) , and the vcom buffer powers up. the max1883/max1884/max1885 do not contain the charge pumps, but the power-up sequence still con- tains the charge pumps startup logic, which appears as a delay (2 ? 4096/fosc) between the step-up con- verter reaching regulation and when the ready signal and vcom buffer are activated. soft-start for the main step-up regulator, soft-start allows a grad- ual increase of the current-limit level during startup to reduce input surge currents. the max1778/max1880 max1885 divide the soft-start period into four phases. during the first phase, the controller limits the current limit to only 0.38a (see electrical characteristics ), approximately a quarter of the maximum current limit supb v supb 4.5v to 13v c buf bufout buf- v bufout 1.2v to (v supb - 1.2v) buf+ 125mv gnd r12 r r r11 v bufout = ( ) v supb r12 r11 + r12 max1778 max1880 max1881 max1882 max1883 max1884 max1885 gm figure 6. vcom buffer block diagram
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer 24 ______________________________________________________________________________________ (i lx(max) ). if the output does not reach regulation within 1ms, soft-start enters phase ii, and the current limit is increased by another 25%. this process is repeated for phase iii. the maximum 1.5a (typ) current limit is reached within 3072 clock cycles or when the output reaches regulation, whichever occurs first (see the startup waveforms in the typical operating characteristics ). for the charge pumps (max1778/max1880/ max1881/max1882 only), soft-start is achieved by con- trolling the rate of rise of the output voltage. both charge-pump output voltages are controlled to be in regulation within 4096 clock cycles, irregardless of out- put capacitance and load, limited only by the charge pump s output impedance. although the max1883/ max1884/max1885 controllers do not include the charge pumps, the soft-start logic still contains the 4096 clock cycle startup periods for both charge pumps. fault trip level (fltset) the max1778/max1880 max1885 feature dual mode operation to allow operation with either a preset fault trip level or an adjustable trip level for the step-up con- verter and positive charge-pump outputs. connect flt- set to gnd to select the preset 0.9 ? v ref fault threshold. the fault trip level may also be adjusted by connecting a voltage divider from ref to fltset (figure 8). for greatest accuracy, the total load on the reference (including current through the negative charge-pump feedback resistors) should not exceed 50a so that vref is guaranteed to be in regulation (see electrical characteristics table). therefore, select r10 in the 100k ? to 1m ? range, and calculate r9 with the following equation: r9 = r10 [(v ref / v fltset ) - 1] where v ref = 1.25v, and v fltset may range from 0.67 x v ref to 0.85 x v ref . fltset s input bias current has a maximum value of 50na. for 1% error, the current through r10 should be at least 100 times the fltset input bias current (i fltset ). fault condition once rdy is low, if the output of the main regulator or either low-power charge pump falls below its fault detection threshold, or if the input drops below its undervoltage threshold, then rdy goes high imped- ance and all outputs shut down; however, the reference remains active. after removing the fault condition, tog- gle shutdown (below 0.8v) or cycle the input voltage (below 0.2v) to clear the fault latch and reactivate the device. the reference fault threshold is 1.05v. for the step-up converter and positive charge-pump, the fault trip level is set by fltset (see fault trip level ). for the negative charge pump, the fault threshold measured at the charge-pump s feedback input (fbn) is 140mv (typ). power ready (rdy) power ready is an open-drain output. when the power- up sequence for the main step-up converter and low- power charge pumps has properly completed, the 14v mosfet turns on and pulls rdy low with a 125 ? (typ) on-resistance. if a fault is detected on any of these three outputs, the internal open-drain mosfet appears as a high impedance. connect a 100k ? pullup resistor between rdy and in for a logic-level output. voltage reference (ref) the voltage at ref is nominally 1.25v. the reference can source up to 50a with good load regulation (see typical operating characteristics). connect a 0.22f ceramic bypass capacitor between ref and gnd. thermal-overload protection thermal-overload protection limits total power dissipa- tion in the max1778/max1880 max1885. when the junction temperature exceeds t j = +160 c, a thermal sensor activates the fault protection, which shuts down the controller, allowing the ic to cool. once the device cools down by 15 c, toggle shutdown (below 0.8v) or cycle the input voltage (below 0.2v) to clear the fault latch and reactivate the controller. thermal-overload protection protects the controller in the event of fault conditions. for continuous operation, do not exceed the absolute maximum junction-temperature rating of t j = +150 c. operating region and power dissipation the max1778/max1880 max1885s maximum power dissipation depends on the thermal resistance of the ic package and circuit board, the temperature difference between the die junction and ambient air, and the rate of any airflow. the power dissipated in the device depends on the operating conditions of each regulator and the buffer. the step-up controller dissipates power across the internal n-channel mosfet as the controller ramps up the inductor current. in continuous conduction, the power dissipated internally can be approximated by: p iv v vd fl rd step up main main in in osc ds on ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? () 22 1 12
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer ______________________________________________________________________________________ 25 where i main includes the primary load current and the input supply currents for the charge pumps (see charge-pump input power and efficiency considerations ), linear regulator, and vcom buffer. the linear regulator generates an output voltage by dis- sipating power across an internal pass transistor, so the power dissipation is simply the load current times the input-to-output voltage differential: when driving an external transistor, the internal linear regulator provides the base drive current. depending on the external transistor s current gain ( ) and the maximum load current, the power dissipated by the internal linear regulator may still be significant: the charge pumps provide regulated output voltages by dissipating power in the low-side n-channel mos- fet, so they could be modeled as linear regulators fol- lowed by unregulated charge pumps. therefore, their power dissipation is similar to a linear regulator: where n is the number of charge-pump stages, v diode is the diodes forward voltage, and v supd is the posi- tive charge-pump diode supply (figure 4). the vcom buffer s power dissipation depends on the capacitive load (c load ) being driven, the peak-to- peak voltage change (v p-p ) across the load, and the load s switching rate: to find the total power dissipated in the device, the power dissipated by each regulator and the buffer must be added together: the maximum allowed power dissipation is 975mw (24- pin tssop) / 879mw (20-pin tssop) or: p max = (t j(max ) - t a ) / ( jb + ba ) where t j - t a is the temperature difference between the controller s junction and the surrounding air, jb (or jc ) is the thermal resistance of the package to the board, and ba is the thermal resistance from the print- ed circuit board to the surrounding air. design procedure main step-up converter output voltage selection adjust the output voltage by connecting a voltage- divider from the output (vmain) to fb to gnd (see typical operating circuit). select r2 in the 10k ? to 50k ? range. calculate r1 with the following equations: r1 = r2 [(v main / v ref ) - 1] where v ref = 1.25v. v main may range from v in to 13v. inductor selection inductor selection depends upon the minimum required inductance value, saturation rating, series resistance, and size. these factors influence the converter s efficiency, maximum output load capability, transient response time, and output voltage ripple. for most applications, values between 4.7h and 22h work best with the controller s switching frequency (tables 1 and 2). the inductor value depends on the maximum output load the application must support, input voltage, output voltage, and switching frequency. with high inductor values, the max1778/max1880 max1885 source high- er output currents, have less output ripple, and enter continuous conduction operation with lighter loads; however, the circuit s transient response time is slower. on the other hand, low-value inductors respond faster to transients, remain in discontinuous conduction oper- ation, and typically offer smaller physical size for a given series resistance and current rating. the equa- tions provided here include a constant lir, which is the ratio of the peak-to-peak ac inductor current to the average dc inductor current. for a good compromise between the size of the inductor, power loss, and out- put voltage ripple, select an lir of 0.3 to 0.5. the inductance value is then given by: l v v vv i f lir min in min main main in min main max osc () () () = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 1 - pp p ppp total step up ldo int neg pos buf () =+ +++ - pvcfv buf p p load load supb = - piv vnv piv vnv v neg neg supn diode neg pos pos supp diode supd pos = () [] = () + [] -- -- 2 2 p i vv v ivv ldo int ldo supl ldo ldoout supl ldoout () . ( ) =+ () [] = - - 07 pivv ldo int ldo supl ldo () ( ) = -
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer 26 ______________________________________________________________________________________ where is the efficiency, f osc is the oscillator frequen- cy (see electrical characteristics ), and i main includes the primary load current and the input supply currents for the charge pumps (see charge-pump input power and efficiency considerations ), linear regulator, and vcom buffer. considering the typical application cir- cuit, the maximum average dc load current (i main(max) ) is 300ma with an 8v output. based on the above equations and assuming 85% efficiency, the inductance value is then chosen to be 4.7h. the inductor s saturation current rating should exceed the peak inductor current throughout the normal operat- ing range. the peak inductor current is then given by: under fault conditions, the inductor current may reach up to 1.85a (i lim(max) ), see electrical characteristics). however, the controller s fast current-limit circuitry allows the use of soft-saturation inductors while still pro- tecting the ic. the inductor s dc resistance may significantly affect efficiency due to the power loss in the inductor. the power loss due to the inductor s series resistance (p lr ) may be approximated by the following equation: where r l is the inductor s series resistance. for best per- formance, select inductors with resistance less than the internal n-channel mosfet on-resistance (0.35 ? typ). use inductors with a ferrite core or equivalent. to mini- mize radiated noise in sensitive applications, use a shielded inductor. output capacitor output capacitor selection depends on circuit stability and output voltage ripple. a 10f ceramic capacitor works well in most applications (tables 1 and 2). additional feedback compensation is required (see feedback compensation ) to increase the margin for stability by reducing the bandwidth further. in cases where the output capacitance is sufficiently large, addi- tional feedback compensation will not be necessary. output voltage ripple has two components: variations in the charge stored in the output capacitor with each lx pulse, and the voltage drop across the capacitor s equivalent series resistance (esr) caused by the cur- rent into and out of the capacitor: where i peak is the peak inductor current (see inductor selection). for ceramic capacitors, the output voltage ripple is typically dominated by v ripple(c) . the voltage rating and temperature characteristics of the output capacitor must also be considered. feedback compensation for stability, add a pole-zero pair from fb to gnd in the form of a compensation resistor (r comp ) in series with a compensation capacitor (c comp ) as shown in figure 2. select r comp to be half the value of r2, the low-side feedback resistor. integrator capacitor the max1778/max1880 max1885 contain an internal current integrator that improves the dc load regulation but increases the peak-to-peak transient voltage (see the load-transient waveforms in the typical operating characteristics ). for highly accurate dc load regula- tion, enable the current integrator by connecting a 470pf ( osc = 1mhz)/1000pf ( osc = 500khz) capacitor to intg. to minimize the peak-to-peak tran- sient voltage at the expense of dc regulation, disable the integrator by connecting intg to ref. when using the max1883/max1884/max1885, connect a 100k ? resistor to gnd when disabling the integrator. input capacitor the input capacitor (c in ) in step-up designs reduces the current peaks drawn from the input supply and reduces noise injection. the value of c in is largely determined by the source impedance of the input sup- ply. high source impedance requires high input capac- itance, particularly as the input voltage falls. since step-up dc-dc converters act as constant-power loads to their input supply, input current rises as input voltage falls. a good starting point is to use the same capacitance value for c in as for c out . vv v v i r and v vv v i cf ripple ripple c ripple esr ripple esr peak esr cout ripple c main in main main out osc , () ( ) () ( ) () =+ ? ? ? ? ? ? ? ? ? ? ? ? ? pr ixv v lr l main main in ? ? ? ? ? ? ? 2 i iv v lir peak main max main in min () () = ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? 1 2 1
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer ______________________________________________________________________________________ 27 rectifier diode use a schottky diode with an average current rating equal to or greater than the peak inductor current, and a voltage rating at least 1.5 times the main output volt- age (v main ). charge pumps (max1778/ max1880/ max1881/max1882 only) selecting the number of charge-pump stages the number of charge-pump stages required to regu- late the output voltage depends on the supply voltage, output voltage, load current, switching frequency, the diode s forward voltage drop, and ceramic capacitor values. for positive charge-pump outputs, the number of required stages may be determined by: where v supd is the positive charge-pump diode supply (figure 4), v diode is the diode s forward voltage drop, and r tx is the charge pump s output impedance. the charge pump s output impedance may be approximat- ed using the following equation: where the charge pump s switching frequency (f chp ) is equal to 0.5 x f osc , the p-channel mosfet s on-resis- tance (r pch(on) ) is 10 ? , and the n-channel mosfet s on-resistance (r nch(on )) is 4 ? (see electrical characteristics ). for negative charge pump outputs, the number of required stages may be determined by: where n neg is rounded up to the nearest integer. n v vvri neg neg supn drop tx load .( ) + ? ? ? ? ? ? -112 rr r cf cf tx pch on nch on x chp out chp ( ) () () =++ ? ? ? ? ? ? + ? ? ? ? ? ? 2 1 1 n vv vvri pos pos supd supp diode tx load .( ) + ? ? ? ? ? ? - -112 circuit #1 circuit #2 circuit #3 circuit #4 circuit #5 v in 3.3v 3.3v 3.3v 5v 5v v main 9v 9v 9v 12v 12v i main(max) 100ma 200ma 200ma 220ma 220ma v neg -5v -5v -5v -5v -5v i neg 2ma 5ma 5ma 5ma 5ma v pos 24v 24v 24v 24v 24v i pos 2ma 5ma 5ma 5ma 5ma l2.2 h4.7 h4.7 h6.8 h6.8 h i peak >1a >1a >1a >1a >1a c out 4.7 f10 f20 f10 f20 f r1 309k ? 309k ? 309k ? 429k ? 429k ? r2 49.9k ? 49.9k ? 49.9k ? 49.9k ? 49.9k ? r comp none none 39k ? * none 20k ? * c comp none none 100pf* none 200pf* table 1. max1778/max1880/max1883 component values (f osc = 1mhz) *r comp and c comp are connected between the step-up converter s output (v main ) and fb.
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer 28 ______________________________________________________________________________________ charge-pump input power and efficiency considerations the charge pumps in the max1778/max1880/ max1881/max1882 provide regulated output voltages by controlling the voltage drop across the low-side n- channel mosfet, so they can be modeled as linear regulators followed by an unregulated charge pump when determining the input power requirements and efficiency. the charge pump only provides charge to the output capacitor during half the period (50% duty cycle), so the input current is a function of the number of stages and the load current: for the positive charge pump, and: for the negative charge pump, where n is the number of charge pump stages. the efficiency characteristics of the max1778/ max1880/max1881/max1882 regulated charge pumps are similar to a linear regulator. it is dominated by quiescent current at low output currents and by the iin supp pos () =+ 1 circuit #6 circuit #7 circuit #8 circuit #9 v in 3.3v 3.3v 3.3v 3.3v v main 9v 9v 9v 9v i main(max) 100ma 100ma 200ma 200ma v neg -5v -5v -5v -5v i neg 2ma 2ma 5ma 5ma v pos 24v 24v 24v 24v i pos 2ma 2ma 5ma 5ma l4.7 h10 h10 h10 h i peak >1a >1a >1a >1a c out 4.7 f10 f10 f20 f r1 309k ? 309k ? 309k ? 309k ? r2 49.9k ? 49.9k ? 49.9k ? 49.9k ? r comp none none none 20k ? * c comp none none none 200pf* table 2. max1881/max1882/max1884/max1885 component values (f osc = 500khz) supplier phone fax inductors coilcraft 847-639-6400 847-639-1469 coiltronics 561-241-7876 561-241-9339 sumida usa 847-956-0666 847-956-0702 toko 847-297-0070 847-699-1194 capacitors avx 803-946-0690 803-626-3123 kemet 408-986-0424 408-986-1442 sanyo 619-661-6835 619-661-1055 taiyo yuden 408-573-4150 408-573-4159 diodes central semiconductor 516-435-1110 516-435-1824 international rectifier 310-322-3331 310-322-3332 motorola 602-303-5454 602-994-6430 nihon 847-843-7500 847-843-2798 zetex 516-543-7100 516-864-7630 table 3. component suppliers *r comp and c comp are connected between the step-up converter s output (v main ) and fb. iin supp pos () =+ 1
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer ______________________________________________________________________________________ 29 input voltage at higher output currents (see typical operating characteristics ). so the maximum efficiency may be approximated by: for the positive charge pump, and: for the negative charge pump, where v supd is the pos- itive charge pump s diode supply (figure 4). output voltage selection adjust the positive output voltage by connecting a volt- age divider from the output (v pos ) to fbp to gnd (see typical operating circuit ). adjust the negative output voltage by connecting a voltage-divider from the output (v neg ) to fbn to ref. select r4 and r6 in the 50k ? to 100k ? range. higher resistor values improve efficiency at low output current but increase output voltage error due to the feedback input bias current. for the negative charge pump, higher resistor values also reduce the load on the reference, which should not exceed 50a for greatest accuracy (including current through the fltset resistors) to guarantee that v ref remains in regulation (see electrical characteristics table). calculate the remaining resistors with the following equations: r3 = r4 [(v pos / v ref ) - 1] r5 = r6 |v neg / v r ef | where v ref = 1.25v. v pos may range from v supp to 40v, and v neg may range from 0v to -40v. flying capacitor increasing the flying capacitor (cx) value increases the output current capability. above a certain point, increasing the capacitance has a negligible effect because the output current capability becomes domi- nated by the internal switch resistance and the diode impedance. the flying capacitor s voltage rating must exceed the following: for the positive charge pump, and: for the negative charge pump, where n is the stage number in which the flying capacitor appears, and v supd is the positive charge pump s diode supply (figure 4). for example, the two-stage positive charge pump in the typical application circuit (figure 1) where v supp = v supd = 8v contains two flying capacitors. the flying capacitor in the first stage (c4) requires a voltage rating over 12v. the flying capacitor in the sec- ond stage (c6) requires a voltage rating over 24v. charge-pump output capacitor increasing the output capacitance or decreasing the esr reduces the output ripple voltage and the peak-to- peak transient voltage. with ceramic capacitors, the output voltage ripple is dominated by the capacitance value. use the following equation to approximate the required capacitor value: where f chp is typically f osc /2 (see electrical characteristics ). charge-pump input capacitor use a bypass capacitor with a value equal to or greater than the flying capacitor. place the capacitor as close to the ic as possible. connect directly to power ground (pgnd). charge-pump rectifier diodes use schottky diodes with a current rating equal to or greater than two times the average charge-pump input current, and a voltage rating at least 1.5 times v supp for the positive charge pump and v supn for the nega- tive charge pump. low-dropout linear regulator (max1778/ max1881/max1883/max1884 only) output voltage selection adjust the linear-regulator output voltage by connecting a voltage-divider from ldoout to fbl to gnd (figure 5). select r8 in the 5k ? to 50k ? range. calculate r7 with the following equation: r7 = r8 [(v ldoout / v fbl ) - 1] where v fbl = 1.25v, and v ldoout may range from 1.25v to (v supl - 300mv). fbl s input bias current is c i fv out load chp ripple vvn cxn neg supn () .( ) > 15 vvvn cxn pos supd supp () . ( ) >+ [] 15 1 - neg v vn neg supn ? pos v vvn pos supd supp ? +
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer 30 ______________________________________________________________________________________ 0.8a (max). for less than 0.5% error due to fbl input bias current (i f bl ), r8 must be less than 8k ? . capacitor selection and regulator stability capacitors are required at the input and output of the max1778/max1881/max1883/max1884 for stable operation over the full temperature range and with load currents up to 40ma. connect a 1f input bypass capacitor (c supl ) between supl and ground to lower the source impedance of the input supply. connect a ceramic capacitor between ldoout and ground, using the following equation to determine the lowest value required for stable operation: for example, with a 5v linear regulator output voltage and a maximum 40ma load, use at least 4f of output capacitance. applications that experience high-current load pulses may require more output capacitance. the esr of the linear regulator s output capacitor (c ldoout ) affects stability and output noise. use out- put capacitors with an esr of 0.1 ? or less to ensure stability and optimum transient response. surface- mount ceramic capacitors are good for this purpose. place c supl and c ldoout as close to the linear regu- lator as possible to minimize the impact of pc board trace inductance. external pass transistor for applications where the linear regulator currents exceed 40ma or where the power dissipation in the ic needs to be reduced, an external npn transistor can be used. in this case, the internal ldo only provides the necessary base drive while the external npn tran- sistor supports the load, so most of the power dissipa- tion occurs across the external transistor s collector and emitter. selection of the external npn transistor is based on three factors: the package s power dissipation, the cur- rent gain ( ), and the collector-to-emitter saturation volt- age (v ce(sat) ). first, the maximum power dissipation should not exceed the transistor s package rating: once the appropriate package type is selected, con- sider the npn transistor s current gain. since the inter- nal ldo cannot source more than 40ma (min), the transistor s current gain must be high enough at the lowest collector-to-emitter voltage to support the maxi- mum output load: for stable operation, place a capacitor (c ldoout ) and a minimum load resistor (r5) at the output of the inter- nal linear regulator (the base of the external transistor) to set the dominant pole: since the ldo cannot sink current, a minimum pull- down resistor (r5) is required at the base of the npn transistor to sink leakage currents and improve the high-to-low load-transient response. under no-load conditions, leakage currents from the internal pass transistor supply the output capacitor (c ldoout ), even when the transistor is off. as the leakage currents increase over temperature, charge may build up on c ldoout , making the linear regulator s output rise above its set point. therefore, r5 must sink at least 100a to guarantee proper regulation. additionally, the minimum load current provided by r5 improves the high-to-low load transients by lowering the impedance seen by c ldoout after the transient occurs. therefore, if large load transients are expected, select r5 so that the minimum load current is 10% of the transistor s maximum base current: alternatively, output capacitance placed on the external linear regulator s output (the emitter) adds a second pole that could destabilize the regulator. a capacitive-divider from the transistor s base to the feedback input (c2 and c3, figure 7) circumvents this second pole by adding a pole-zero pair. furthermore, to minimize excessive over- shoot, the capacitive-divider s ratio must be the same as the resistive-divider s ratio. once the output capacitor is selected, using the following equations to determine the required capacitive-divider values: cc cr r c cc r rr v v ldo ref ldo 23 100 1 4 3 2 23 4 34 + + ? ? ? ? ? ? + = + = r vv i vv i ldo ldoout min ldo mi n load max 5 07 01 07 . . ( .) () ( ) = + = + ? ? ? ? cms v x vv r i ldoout ldo ldo load max min . . () ? ? ? ? ? ? + + ? ? ? ? ? ? 05 1 07 5 min load max ima ma () -40 40 pv v xi collector ldo load max ( ) () =? cmsx i v ldoout ldoout max ldoout . () ? ? ? ? ? ? ? ? 05
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer ______________________________________________________________________________________ 31 input-output (dropout) voltage and startup a linear regulator s minimum input-to-output voltage dif- ferential (dropout voltage) determines the lowest use- able supply voltage. because the max1778/ max1881/max1883/max1884 use an internal pnp transistor (or external npn transistor), their dropout voltage is a function of the transistor s collector-to-emit- ter saturation voltage (see typical operating characteristics ). the linear regulator s quiescent cur- rent increases when in dropout. the internal linear regulator will try to start up once its supply voltage (v supl ) exceeds 4v. when the linear regulator powers up, the linear regulator may be in dropout if the linear regulator s output set voltage is higher than its input supply voltage. therefore, during this brief period, the linear regulator draws additional supply current until the input supply voltage exceeds the output set voltage plus the pass transistor s satura- tion voltage (v ldo(set ) + v ce(sat) ). vcom buffer (operational transconductance amplifier) buffer output voltage and capacitor selection the positive input (buf+) features dual mode opera- tion. connect buf+ to gnd for the preset vsupb/2 output voltage, set by an internal 50% resistive-divider. adjust the amplifier s output voltage by connecting a voltage-divider from supb to buf+ to gnd (figure 6). select r12 in the 10k ? to 100k ? range. calculate r11 with the following equation: where v supb may range from 4.5v to 13v, and v buf+ may range from 1.2v to (v supb - 1.2v). connect a mini- mum 1f ceramic capacitor from bufout to ground. pc board layout and grounding careful pc board layout is extremely important for proper operation. follow the following guidelines for good pc board layout: 1) place the main step-up converter output diode and output capacitor less than 0.2in (5mm) from the lx and pgnd pins with wide traces and no vias. 2) separate analog ground and power ground. the ground connections for the step-up converter s and charge pump s input and output capacitors should be connected to the power ground plane. the lin- ear regulator s and vcom buffer s input and output capacitors should be connected to a separate power-ground path, star-connected to the pgnd pin to minimize voltage drops. when using multi- layer boards, the top layer should contain the boost rr v v supb buf 11 12 1 = ? ? ? ? ? ? ? ? ? ? ? ? ? ? + - in shdn ldoout lx l1 6.8 h input v in = 3.3v c1 0.22 f c out (2) 4.7 f c in 4.7 f r1 274k ? r2 49.9k ? fb gnd fbl ref q1 intg pgnd c ref 0.22 f max1778 max1883 (max1881)* (max1884)* r3 49.9k ? r4 49.9k ? c ldo 1 f c3 0.01 f c2 0.01 f c ldoout 4.7 f c ldoin 1 f r5 1.5k ? main v main = 8v ldo v ldo = 2.5v supl figure 7. external linear regulator
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer 32 ______________________________________________________________________________________ regulator and charge-pump power ground plane, and the inner layer should contain the analog ground plane and power-ground plane/path for the v com buffer and ldo. connect all three ground planes together at one place near the pgnd pin. 3) locate all feedback resistive-dividers as close to their respective feedback pins as possible. the voltage-divider s center trace should be kept short. avoid running any feedback trace near the lx switching node or the charge-pump drivers. the resistive-dividers ground connections should be to analog ground (gnd). 4) when using multilayer boards, separate the top sig- nal layer and bottom signal layer with a ground plane between to eliminate capacitive coupling between fast-charging nodes on the top layer and high-impedance nodes on the bottom layer. the fast-charging nodes, such as the lx and charge- pump driver nodes, should not have any other traces or ground planes near by. 5) keep the charge-pump circuitry as close to the ic as possible, using wide traces and avoiding vias when possible. place 0.1f ceramic bypass capacitors near the charge-pump input pins (supp and supn) to the pgnd pin. 6) to maximize output power and efficiency and mini- mize output ripple voltage, use extra wide, power ground traces, and solder the ic s power ground pin directly to it. refer to the max1778/max1880-max1885 evaluation kit for an example of proper board layout. in buffer output v bufout = v supb /2 positive v pos = 20v shdn rdy supl ldoout supn supp drvp fbp lx l1 10 h input v in = 5v c1 0.22 f c6 1 f c6 0.01 f c7 0.01 f c3 1.0 f c ref 0.22 f c2 0.1 f c buf 1.0 f c5 1.0 f c comp 470pf c out (2) 10 f c4 0.1 f c in (2) 4.7 f c ldoout 4.7 f r rdy 100k ? r8 1.5k ? r8 10k ? r5 316k ? r9 30k ? r3 750k ? r4 49.9k ? r1 86.6k ? r2 10k ? r comp 4.7k ? r10 100k ? r6 49.9k ? r7 16.4k ? negative v neg = -8v to logic fb bufout buf- buf+ fltset gnd tgnd fbl drvn fbn ref intg pgnd supb max1778 ldo v ldo = 3.3v q1 ref main v main = 12v figure 8. 5v input monitor application
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer ______________________________________________________________________________________ 33 applications information low-profile components notebook applications generally require low-profile components, potentially limiting the circuit s perfor- mance. for example, low-profile inductors typically have lower saturation ratings and more series resis- tance, limiting output current and efficiency. low-profile capacitors have lower voltage ratings for a given capacitance value, so 3.3f low-profile capacitors with voltage ratings greater than 10v were not available at the time of publication. desktop monitors monitor applications do not have the same component height restrictions associated with laptops, allowing more flexibility in component selection (figure 8). larger output capacitors with higher voltage ratings allow configurations with output voltages above 10v. additionally, physically larger inductors with less series resistance and higher saturation ratings provide more output current and higher efficiency. input voltage above and below the output voltage combining the step-up converter and linear regulator as shown in figure 9 provides output voltage regulation above and below the input voltage. supplied by the step-up converter, the linear regulator output provides a constant output voltage (v ldo ). when the input volt- age exceeds the main step-up converter s nominal out- put voltage, the controller stops switching but the linear regulator maintains the output voltage. when the input voltage drops below the output voltage, the step-up in buffer output v bufout = v supb /2 positive v pos = 24v shdn rdy buf- bufout supn supp lx l1 6.8 h power input v batt = 10v to 15v input v in = 3.3v to 5v c1 0.1 f c ldo (2) 3.3 f c6 0.1 f c7 0.1 f c3 1.0 f c buf 1.0 f c intg 470pf c2 0.1 f c out (3) 3.3 f c4 0.1 f c in 4.7 f c ldoout 3.3 f r rdy 100k ? r10 100k ? r5 475k ? r3 909k ? r8 49.9k ? r1 511k ? r2 49.9k ? r4 49.9k ? r7 470k ? r6 49.9k ? r9 6.8k ? negative v neg = -12v to logic fb fbl supl ldoout buf+ fbp drvp gnd tgnd fbn drvn ref fltset intg pgnd supb c ref 0.22 f max1778 ldo v ldo = 13v q1 c5 1.0 f r9 30k ? figure 9. input voltage above and below the output voltage
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer 34 ______________________________________________________________________________________ converter steps up the input voltage so that the linear regulator will not drop out. therefore, to guarantee that the external pass transistor does not saturate, the step- up converter s output voltage must be set above the lin- ear regulator s output voltage plus the transistor s saturation rating (v main v ldo + v sat ). power-up sequencing and fault protection the max1778/max1880 max1885 s fault protection cannot be activated until the power-up sequence is successfully completed and the power ready output goes low. therefore, faults on the main output or posi- tive charge-pump output could damage the controller or external components. additional fault protection may be added as shown in figure 10. the external mosfet and pnp transistor isolate the positive outputs during startup. when the controller finishes the power-up sequence, the power-ready output goes low, turning on the pnp transistor. any fault on the positive charge- pump output will pull down the charge pump s output voltage and trigger the fault protection; otherwise, the mosfet s gate slow charges. once the mosfet turns on, any faults on the main step-up converter s output will pull down the main output voltage and trigger the fault protection. vcom buffer startup the vcom buffer does not include soft-start. therefore, once the vcom buffer turns on, it draws high surge currents while charging the output capacitance. in some applications, the buffer s high startup surge current could potentially trip the fault detection circuit, forcing the controller to shut down. in these cases, adding a soft-start resistive divider between supb and bufout reduces the startup surge current and voltage drops associated with this load (figure 11), as shown in in system positive v pos(sys) = 20v startup positive v pos(start) = 20v input v in = 3.3v shdn supp lx l1 6.8 h input v in = 3.3v c1 0.22 f c5 1.0 f c7 1.0 f q2 q3 c out (2) 3.3 f c4 0.1 f c in 4.7 f r10 100k ? r rdy 5.1k ? r1 274k ? r2 49.9k ? r7 10k ? fb rdy fbp drvp gnd tgnd ref fltset intg pgnd c ref 0.22 f max1778 c8 3.3 f system main v main(sys) = 8v startup main v main(start) = 8v c10 0.1 f c6 0.1 f r8 100k ? r3 750k ? r4 49.9k ? r9 30k ? figure 10. power-up sequencing and fault protection;
the typical operating characteristics . set the resistive divider to precharge bufout, matching the buffer s output set voltage: these resistor values are selected to charge the output capacitor close to the output set voltage before the buffer starts up: crr f bufout osc (||) 34 5000 rr v v supb bufout 34 1 = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer ______________________________________________________________________________________ 35 part step-up switching frequency (h z ) dual charge pumps linear regulator max1778 1m yes yes max1880 1m yes no max1881 500k yes yes max1882 500k yes no max1883 1m no yes max1884 500k no yes max1885 500k no no selector guide in buffer output v bufout = v supb /2 shdn supb lx l1 6.8 h input v in = 3.3v c1 0.22 f c out (2) 4.7 f c in 4.7 f r1 274k ? r2 49.9k ? fb bufout gnd buf+ buf- ref intg pgnd c ref 0.22 f max1778 c supb 1.0 f c buf 1.0 f r3 10k ? r4 10k ? main v main = 8v r3 = r4 [( ) -1 ] v supb v bufout figure 11. vcom buffer soft-start;
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer 36 ______________________________________________________________________________________ typical operating circuit in buffer output positive shdn rdy supl ldoout supn supp drvp fbp lx input ldo output negative to logic fb bufout buf- buf+ fltset gnd tgnd fbl drvn fbn ref intg pgnd supb max1778 main
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer ______________________________________________________________________________________ 37 pin configurations 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 tgnd lx pgnd buf+ in intg fb top view drvp supp drvn supn gnd bufout supb buf- 16 15 14 13 9 10 11 12 fltset fbl ldoout supl fbn fbp ref 24 tssop max1778 max1881 rdy shdn 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 tgnd lx pgnd buf+ in intg fb drvp supp drvn supn gnd bufout supb buf- 16 15 14 13 9 10 11 12 fltset n.c. n.c. n.c. fbn fbp ref 24 tssop max1880 max1882 rdy shdn 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 tgnd lx pgnd buf+ in intg fb top view n.c. n.c. fltset fbl gnd bufout supb buf- 12 11 9 10 ldoout supl ref max1883 max1884 20 tssop rdy shdn 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 tgnd lx pgnd buf+ in intg fb n.c. n.c. fltset n.c. gnd bufout supb buf- 12 11 9 10 n.c. n.c. ref max1885 20 tssop rdy shdn
max1778/max1880?ax1885 quad-output tft lcd dc-dc converters with buffer maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 38 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2001 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information chip information transistor count: 3739 tssop,no pads.eps

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